Recently transistors having a short gate length have been used in association with high integration of semiconductor integrated circuits. A memory circuit and the like comprising such transistors having a short gate length adopts a circuit for generating an internal power source voltage ranging 3 through 4 voltages for internal components by a constant voltage generating circuit provided therein in addition to an external power source of 5 volts in view of reliability. Accordingly, circuits to which the external power source voltage is supplied and circuits to which internal power source voltage is supplied coexist in this memory.
For example, circuits such as first stage transistors to which addresses, clocks and data are inputted and an output transistors, which are connected with input/output terminals are supplied with a power source voltage different from a voltage supplied to the other internal circuits.
FIG. 1 is a circuit diagram showing a prior art different power source interface.
As shown in FIG. 1, such interface circuit comprises inverter circuits 7, 5 and 8 which are in series connected for connecting a first power source (V.sub.I) circuit 1 with a second power source (V.sub.E) circuit 2. The inverter circuit 7 is supplied with a voltage V.sub.I(V) from a first power source V.sub.CCI while the inverter circuits 5 and 8 are supplied with a voltage V.sub.E(V) higher than the voltage V.sub.I of the first power source. Each of inverter circuits 7, 5 and 8 comprises pairs of P and N channel MOS transistors Q1, Q2; Q5, Q6; and Q9, Q10, respectively. References N1, N2, N4 and N5 represent nodes.
It is assumed herein that voltages V.sub.I and V.sub.E have relation V.sub.E &gt;V.sub.I and there is a relation V.sub.E -V.sub.I .gtoreq..vertline.V.sub.TP .vertline. wherein V.sub.TP represents a threashold voltages of the P channel MOS transistors.
FIG. 2 is a graph showing the voltage characteristics at each node in the interface circuit shown in FIG. 1.
As shown in FIG. 2, the voltages at anodes N1 and N2, N4 and N5 exhibit opposite polarities with each other.
A case in which the node N1 is at an "L" level, that is 0V will be described at this time the transistor Q1 of the inverter circuit 7 is turned ON and the transistor Q2 is turned OFF and the note N2 is at an "H" level. Since the transistor Q6 of the inverter circuit 5 is turned ON and there is a relation V.sub.E -V.sub.1 .gtoreq..vertline.V.sub.TP .vertline., the transistor Q5 is turned ON. Therefore, the potential of the node N4 is .alpha.(V) which is determined by the ratio of capacities of the transistors Q5 and Q6. If the transistor Q9 of the inverter circuit 8 is turned ON and the voltage .alpha. satisfies a relation .alpha.&lt; V.sub.TN wherein represents the threshold voltage of the N channel MOS transistor, the transistor Q10 would be turned ON and the node N5 would assume V.sub.E(V). If .alpha..gtoreq.V.sub.TN, the transistor Q10 is turned ON, the voltage at the node N5 assumes V.sub.E -.beta. (V) which is determined by the ratio of the capacities of the transistors Q9 and Q10.
When the node N1 is at on "W" level, that is V.sub.I(V), the transistor Q1 of the inverter circuit 7 is turned OFF, that is, at 0 volt.
FIG. 3 is a circuit diagram showing another prior art different power source interface circuit.
As shown in FIG. 3, such an interface circuit comprises a plurality of first power source operating circuits (V.sub.CCI) 1. In this case, the interface circuit further includes a second power source operating circuit 2 having a voltage V.sub.CCE higher than the voltage V.sub.CCI of the first power source and an NOR circuit 9 comprising P channel MOS transistors Q11, Q12 and N channel MOS transistor Q13 and Q14.
That is, the interface circuit shown in FIG. 3 comprises a two-input NOR circuit 9 which is connected with the outputs of the inverter circuits 7A and 7B of the first power source operating circuit 1 and an inverter circuit 8 which is in series connected with the NOR circuit 9. Since the transistor Q11 and Q12 are always turned ON in the interface circuit independently of the potentials of the nodes N2A and N2B are at an "L" level.
When V.sub.CCE -V.sub.CCI .gtoreq..vertline.V.sub.TP .vertline. in the above mentioned prior art difference power source interface circuit wherein V.sub.CCI is a voltage supplied from the first voltage source circuit and V.sub.CCE is a voltage supplied from the second power source operating circuit, which is lower than the voltage V.sub.CCE, the channel MOS transistor having a gate electrode to which an output of a circuit supplied with the voltage V.sub.CCI and a source electrode which is supplied with the voltage V.sub.CCE is always turned ON independently of the potential of the gate. Accordingly, there is a disadvantage that a through-current flows through the second power circuit which supplies the voltage V.sub.CCE.
In other words, the prior art shown in FIG. 4 has a disadvantage that a through-current always flows through the inverter circuit 5. Since the "L" level output will not completely fall to zero due to the ratio of capabilities of the transistors Q5 and Q6, making the rating of the transistor Q5 larger than that of the transistor Q6, the "L" level output becomes an intermediate level, resulting in that a through current will also flow through the inverter circuit 8 at the next stage. This may offer a disadvantage of possible malfunction in addition to an increase in consumed current due to the through-current.
Therefore, it is an object of the present invention to provide an interface circuit for different power source which cannot only avoid such through-current, but also avoid an increase in consummed current and malfunction.